Mobile devices have become the largest market segment for semiconductor content in the electronics industry. Consumers are demanding more from their mobile devices: sleeker form factors, faster connectivity, richer and bigger displays, and better multimedia capabilities. In turn, their devices are demanding more processing horsepower. To meet this demand, the mobile industry is continually innovating to deliver the increasing performance while maintaining thermal efficiency and delivering longer battery life. Despite the advancements in device capabilities, long battery life remains the number one requested smartphone feature by consumers. This makes it mandatory for designers to incorporate more complex power-management techniques into their integrated circuits.
Advances in semiconductor fabrication technology are the key enabler for integration of more complex functions in systems-on-chips (SoC) in consumer electronics and other applications. However, scaling of MOS transistors to achieve higher functional density comes at a cost. Gate dielectrics are now only a few atomic layers thick. Leakage from porous gate dielectrics and shorter channel lengths can cause the static power dissipation of many chips to be greater than the dynamic power dissipation from active circuit operation, making the power management task even more challenging to designers.
One approach to reduce static power dissipation is by turning off large circuit blocks during idle periods. This power gating approach, however, may lead to high impedance (high-Z) nodes. Some of these high impedance nodes can result in excessive current paths. FIG. 2 illustrates an example of the high-Z node problem. In the circuit shown in the figure, two transistor pairs 210/220 and 240/250 operate as two invertors, respectively. Transistor 230 serves as a gating device between the two invertors. If node 215 is at 0V, node 225 is at Vdd due to inversion by the transistor pair 210/220. If node 235 is at Vdd, the transistor 230 is switched on and node 245 has the logic “1”. The node 245 can be disconnected from the node 235 by switching off the transistor 230. This is achieved by changing the voltage at the node 235 to 0V. In such a state, any switching activities happening at and before the node 235 will not affect the transistors 240/250 and the part of the circuit driven by them in an ideal world.
In reality, however, the node 245 may not be able to retain the logic “1” over time because of leakage current through parasitic elements of the circuit. This may cause the PMOS (240) and NMOS (250) transistors to drift to a highly conductive state. A potentially destructive condition may result, with the power supply of the inverter 240/250 becoming essentially short-circuited to ground. The large time constant of the voltage drift at the node 245 exacerbates the power dissipation. One solution is to include a bus keeper or retention register to properly isolate high-impedance nodes from the active circuitry. The solution requires identification of high-impedance nodes in a circuit design.
To identify high-impedance nodes, a conventional method relies on calculating equivalent resistance at the node of interest: applying a stimulus current source; determining the voltage value at the node; and calculating the equivalent resistance by dividing the voltage value by the current value of the current source. This method is time-consuming due to its serial nature. The process has to be performed for each node of interest separately and there may be hundreds or thousands of nodes to check in a large design. Another drawback relates to its assumption that the node of interest is a Hi-Z node. This may lead to identification of some Hi-Z nodes that do not cause power dissipation problems. Detailed explanation is provided below.